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elpida memory, inc. is a joint venture dram company of nec corporation and hitachi, ltd. HB52F649E1-75b 512 mb registered sdram dimm 64-mword 72-bit, 133 mhz memory bus, 1-bank module (18 pcs of 64 m 4 components) pc133sdram e0021h20 (ver. 2.0) aug. 20, 2001 (k) description the HB52F649E1 belongs to 8-byte dimm (dual in-line memory module) family, and has been developed as an optimized main memory solution for 8-byte processor applications. the HB52F649E1 is a 64m 72 1-bank synchronous dynamic ram registered module, mounted 18 pieces of 256-mbit sdram (hm5225405btt) sealed in tsop package, 1 piece of pll clock driver, 3 pieces of register driver and 1 piece of serial eeprom (2-kbit) for presence detect (pd). an outline of the HB52F649E1 is 168-pin socket type package (dual lead out). therefore, the HB52F649E1 makes high density mounting possible without surface mount technology. the HB52F649E1 provides common data inputs and outputs. decoupling capacitors are mounted beside each tsop on the module board. features ? fully compatible with : jedec standard outline 8-byte dimm ? 168-pin socket type package (dual lead out) ? outline: 133.35 mm (length) 43.18 mm (height) 4.00 mm (thickness) ? lead pitch: 1.27 mm ? 3.3 v power supply ? clock frequency: 133 mhz (max) ? lvttl interface ? data bus width: 72 ecc ? single pulsed ras ? 4 banks can operates simultaneously and independently ? burst read/write operation and burst read/single write operation capability ? programmable burst length: 1/2/4/8 ? 2 variations of burst sequence ? sequential ? interleave
HB52F649E1-75b data sheet e0021h10 2 ? programmable ce latency : 4 (133 mhz) : 3 (100 mhz) ? byte control by dqmb ? refresh cycles: 8192 refresh cycles/64 ms ? 2 variations of refresh ? auto refresh ? self refresh ordering information type no. frequency ce latency package contact pad HB52F649E1-75b* 1 133 mhz 4 168-pin dual lead out socket type gold note: 1. 100 mhz operation at ce latency = 3. pin arrangement 1 pin 10 pin 11 pin 40 pin 41 pin 84 pin 85 pin 94 pin 95 pin 124 pin 125 pin 168 pin
HB52F649E1-75b data sheet e0021h10 3 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 nc 86 dq32 128 cke0 3 dq1 45 s2 87 dq33 129 nc 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6v cc 48 nc 90 v cc 132 nc 7 dq4 49 v cc 91 dq36 133 v cc 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 cb2 94 dq39 136 cb6 11 dq8 53 cb3 95 dq40 137 cb7 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v cc 101 dq45 143 v cc 18 v cc 60 dq20 102 v cc 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 nc 104 dq47 146 nc 21 cb0 63 nc 105 cb4 147 rege 22 cb1 64 v ss 106 cb5 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 26 v cc 68 v ss 110 v cc 152 v ss 27 w 69 dq24 111 ce 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 s0 72 dq27 114 nc 156 dq59 31 nc 73 v cc 115 re 157 v cc 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63
HB52F649E1-75b data sheet e0021h10 4 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 ck2 121 a9 163 ck3 38 a10 (ap) 80 nc 122 ba0 164 nc 39 ba1 81 wp 123 a11 165 sa0 40 v cc 82 sda 124 v cc 166 sa1 41 v cc 83 scl 125 ck1 167 sa2 42 ck0 84 v cc 126 a12 168 v cc pin description pin name function a0 to a12 address input ? row address a0 to a12 ? column address a0 to a9, a11 ba0/ba1 bank select address dq0 to dq63 data input/output cb0 to cb7 check bit (data input/output) s0 , s2 chip select input re row enable (ras) input ce column enable (cas) input w write enable input dqmb0 to dqmb7 byte data mask ck0 to ck3 clock input cke0 clock enable input wp write protect for serial pd rege* 1 register/buffer enable sda data input/output for serial pd scl clock input for serial pd sa0 to sa2 serial address input v cc primary positive power supply v ss ground nc no connection note: 1. rege v ih : register mode. rege v il : buffer mode.
HB52F649E1-75b data sheet e0021h10 5 serial pd matrix* 1 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 0 number of bytes used by module manufacturer 1000000080 128 1 total spd memory size 0000100008 256 byte 2 memory type 0000010004 sdram 3 number of row addresses bits 000011010d 13 4 number of column addresses bits 000010110b 11 5 number of banks 0000000101 1 6 module data width 0100100048 72 bit 7 module data width (continued) 0000000000 0 (+) 8 module interface signal levels 0000000101 lvttl 9 sdram cycle time (highest ce latency) 7.5 ns 0111010175 cl = 3 10 sdram access from clock (highest ce latency) 5.4 ns 0101010054 * 5 11 module configuration type 0000001002 ecc 12 refresh rate/type 1000001082 normal (7.8125 ?) self refresh 13 sdram width 0000010004 64m 4 14 error checking sdram width 0000010004 4 15 sdram device attributes: minimum clock delay for back-to- back random column addresses 0000000101 1 clk 16 sdram device attributes: burst lengths supported 000011110f 1, 2, 4, 8 17 sdram device attributes: number of banks on sdram device 0000010004 4 18 sdram device attributes: ce latency 0000011006 2/3 19 sdram device attributes: s latency 0000000101 0 20 sdram device attributes: w latency 0000000101 0 21 sdram device attributes 000111111f registered
HB52F649E1-75b data sheet e0021h10 6 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 22 sdram device attributes: general 000011100e v cc ?10% 23 sdram cycle time (2nd highest ce latency) 10 ns 10100000a0 cl = 2 * 5 24 sdram access from clock (2nd highest ce latency) 6 ns 0110000060 25 sdram cycle time (3rd highest ce latency) undefined 0000000000 26 sdram access from clock (3rd highest ce latency) undefined 0000000000 27 minimum row precharge time 0001010014 20 ns 28 row active to row active min 000011110f 15 ns 29 re to ce delay min 0001010014 20 ns 30 minimum re pulse width 001011012d 45 ns 31 density of each bank on module 1000000080 1 bank 512m byte 32 address and command signal input setup time 0001010115 1.5 ns* 5 33 address and command signal input hold time 0000100008 0.8 ns* 5 34 data signal input setup time 0001010115 1.5 ns* 5 35 data signal input hold time 0000100008 0.8 ns* 5 36 to 61 superset information 0000000000 future use 62 spd data revision code 0000001002 jedec2 63 checksum for bytes 0 to 62 10101100ac 172 64 manufacturer? jedec id code 0000011107 hitachi 65 to 71 manufacturer? jedec id code 0000000000 72 manufacturing location * 2 (ascii- 8bit code) 73 manufacturer s part number 0100100048 h 74 manufacturer s part number 0100001042 b 75 manufacturer s part number 0011010135 5 76 manufacturer s part number 0011001032 2
HB52F649E1-75b data sheet e0021h10 7 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 77 manufacturer s part number 0100011046 f 78 manufacturer s part number 0011011036 6 79 manufacturer s part 0011010034 4 80 manufacturer s part number 0011100139 9 81 manufacturer s part number 0100010145 e 82 manufacturer s part number 0011000131 1 83 manufacturer s part number 001011012d 84 manufacturer s part number 0011011137 7 85 manufacturer s part number 0011010135 5 86 manufacturer s part number 0100001042 b 87 manufacturer s part number 0010000020 (space) 88 manufacturer s part number 0010000020 (space) 89 manufacturer s part number 0010000020 (space) 90 manufacturer s part number 0010000020 (space) 91 revision code 0011000030 initial 92 revision code 0010000020 (space) 93 manufacturing date year code (bcd) 94 manufacturing date week code (bcd) 95 to 98 assembly serial number * 3 99 to 125 manufacturer specific data * 4 126 reserved (intel specification frequency) 0110010064 127 reserved (intel specification ce # latency support) 1000011187 notes: 1. all serial pd data are not protected. 0: serial data, driven low , 1: serial data, driven high . 2. byte72 is manufacturing location code. (ex: in case of japan, byte72 is 4ah. 4ah shows j on ascii code.) 3. bytes 95 through 98 are assembly serial number. 4. all bits of 99 through 125 are not defined ( 1 or 0 ). 5. these specifications are defined based on component specification, not module.
HB52F649E1-75b data sheet e0021h10 8 block diagram i/o0 to i/o3 dqmb dq0 to dq3 * d0 to d17: hm5225405 pll: 2510 register: 162834 u0: 2-k bit eeprom v cc (d0 to d17, u0) v ss (d0 to d17, u0) serial pd sda wp 47 k ? a0 a1 a2 sa0 sa1 sa2 v ss v ss v cc scl u0 sda scl notes: 1. the sda pull-up resistor is required due to the open-drain/open-collector output. 2. the scl pull-up resistor is recommended because of the normal scl line inacitve 4 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 0.22 f 18 pcs 2.2 f 2 pcs 0.0022 f 24 pcs rs0 cs d0 rdqmb0 "high" state. i/o0 to i/o3 dqmb dq4 to dq7 4 cs d1 i/o0 to i/o3 dqmb dq8 to dq11 4 cs d2 rdqmb1 i/o0 to i/o3 dqmb dq12 to dq15 4 cs d3 i/o0 to i/o3 dqmb cb0 to cb3 4 cs d4 i/o0 to i/o3 dqmb dq32 to dq35 4 cs d9 rdqmb4 i/o0 to i/o3 dqmb dq36 to dq39 4 cs d10 i/o0 to i/o3 dqmb dq40 to dq43 4 cs d11 rdqmb5 i/o0 to i/o3 dqmb dq44 to dq47 4 cs d12 i/o0 to i/o3 dqmb cb4 to cb7 4 cs d13 i/o0 to i/o3 dqmb dq16 to dq19 4 rs2 cs d5 rdqmb2 i/o0 to i/o3 dqmb dq20 to dq23 4 cs d6 i/o0 to i/o3 dqmb dq24 to dq27 4 cs d7 rdqmb3 i/o0 to i/o3 dqmb dq28 to dq31 4 cs d8 i/o0 to i/o3 dqmb dq48 to dq51 4 cs d14 rdqmb6 i/o0 to i/o3 dqmb dq52 to dq55 4 cs d15 i/o0 to i/o3 dqmb dq56 to dq59 4 cs d16 rdqmb7 i/o0 to i/o3 dqmb dq60 to dq63 4 cs d17 s0 , s2 dqmb0 to dqmb7 ba0 to ba1 a0 to a12 re ce cke0 w rs0 , rs2 rdqmb0 to rdqmb7 rba0 to rba1 -> ba0 to ba1: sdrams d0 to d17 ra0 to ra12 -> a0 to a12: sdrams d0 to d17 rras -> ras : sdrams d0 to d17 rcas -> cas : sdrams d0 to d17 rcke0 -> cke: sdrams d0 to d17 rw -> we : sdrams d0 to d17 10 k ? v cc r e g i s t e r rege pll ck 10 ? pll 12 pf ck0 10 ? 12 pf v ss v ss ck1 to ck3
HB52F649E1-75b data sheet e0021h10 9 absolute maximum ratings parameter symbol value unit note voltage on any pin relative to v ss v t 0.5 to v cc + 0.5 ( 4.6 (max)) v1 supply voltage relative to v ss v cc 0.5 to +4.6 v 1 short circuit output current iout 50 ma power dissipation p t 18.0 w operating temperature topr 0 to +55 c storage temperature tstg 50 to +100 c note: 1. respect to v ss dc operating conditions (ta = 0 to +55?) parameter symbol min max unit notes supply voltage v cc 3.0 3.6 v 1, 2 v ss 00v3 input high voltage v ih 2.0 v cc v 1, 4 input low voltage v il 0 0.8 v 1, 5 notes: 1. all voltage referred to v ss 2. the supply voltage with all v cc pins must be on the same level. 3. the supply voltage with all v ss pins must be on the same level. 4. v ih (max) = v cc + 2.0 v for pulse width 3 ns at v cc . 5. v il (min) = v ss ? 2.0 v for pulse width 3 ns at v ss .
HB52F649E1-75b data sheet e0021h10 10 dc characteristics (ta = 0 to 55 c, v cc = 3.3 v 0.3 v, v ss = 0 v) HB52F649E1-75b pc133 ce latency = 4 pc100 ce latnecy = 3 parameter symbol min max min max unit test conditions notes operating current i cc1 2675 2675 ma burst length = 1 t rc = min 1, 2, 3 standby current in power down i cc2p 749 749 ma cke = v il , t ck = 12 ns 6 standby current in power down (input signal stable) i cc2ps 731 731 ma cke = v il , t ck = 7 standby current in non power down i cc2n 1055 1055 ma cke, s = v ih , t ck = 12 ns 4 active standby current in power down i cc3p 767 767 ma cke = v il , t ck = 12 ns 1, 2, 6 active standby current in non power down i cc3n 1235 1235 ma cke, s = v ih , t ck = 12 ns 1, 2, 4 burst operating current i cc4 3035 2405 ma t ck = min, bl = 4 1, 2, 5 refresh current i cc5 4655 4655 ma t rc = min 3 self refresh current i cc6 749 749 ma v ih v cc 0.2 v v il 0.2 v 8 input leakage current i li 10 10 10 10 a 0 vin v cc output leakage current i lo 10 10 10 10 a 0 vout v cc dq = disable output high voltage v oh 2.4 2.4 vi oh = 4 ma output low voltage v ol 0.4 0.4 v i ol = 4 ma notes: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. one bank operation. 3. input signals are changed once per one clock. 4. input signals are changed once per two clocks. 5. input signals are changed once per four clocks. 6. after power down mode, ck operating current. 7. after power down mode, no ck operating current. 8. after self refresh mode set, self refresh current.
HB52F649E1-75b data sheet e0021h10 11 capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) parameter symbol max unit notes input capacitance (address) c i1 23 pf 1, 2, 4 input capacitance ( re , ce , w )c i2 23 pf 1, 2, 4 input capacitance (cke) c i3 23 pf 1, 2, 4 input capacitance ( s )c i4 15 pf 1, 2, 4 input capacitance (ck) c i5 40 pf 1, 2, 4 input capacitance (dqmb) c i6 15 pf 1, 2, 4 input/output capacitance (dq) c i/o1 15 pf 1, 2, 3, 4 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. measurement condition: f = 1 mhz, 1.4 v bias, 200 mv swing. 3. dqmb = v ih to disable data-out. 4. this parameter is sampled and not 100% tested. ac characteristics (ta = 0 to 55 c, v cc = 3.3 v 0.3 v, v ss = 0 v) HB52F649E1-75b pc133 ce latency = 4 pc100 ce latency = 3 parameter symbol pc100 symbol min max min max unit notes system clock cycle time t ck tclk 7.5 10 ns 1 ck high pulse width t ckh tch 3.4 4 ns 1 ck low pulse width t ckl tcl 3.4 4 ns 1 access time from ck t ac tac 6.3 6.9 ns 1, 2 data-out hold time t oh toh 1.8 2.1 ns 1, 2 ck to data-out low impedance t lz 1.1 1.1 ns 1, 2, 3 ck to data-out high impedance t hz 6.3 6.9 ns 1, 4 data-in setup time t ds tsi 2.4 2.9 ns 1 data in hold time t dh thi 1.7 1.9 ns 1 address setup time t as tsi 1.9 2.6 ns 1 address hold time t ah thi 1.5 1.6 ns 1 cke setup time t ces tsi 1.9 2.6 ns 1, 5 cke setup time for power down exit t cesp tpde 1.9 2.6 ns 1 cke hold time t ceh thi 1.5 1.6 ns 1
HB52F649E1-75b data sheet e0021h10 12 ac characteristics (ta = 0 to 55 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (cont) HB52F649E1-75b pc133 ce latency = 4 pc100 ce latency = 3 parameter symbol pc100 symbol min max min max unit notes command setup time t cs tsi 1.9 2.6 ns 1 command hold time t ch thi 1.5 1.6 ns 1, 5 ref/active to ref/active command period t rc trc 67.5 70 ns 1 active to precharge command period t ras tras 45 120000 50 120000 ns 1 active command to column command (same bank) t rcd trcd 20 20 ns 1 precharge to active command period t rp trp 20 20 ns 1 write recovery or data-in to precharge lead time t dpl tdpl 7.5 10 ns 1 active (a) to active (b) command period t rrd trrd 15 20 ns 1 transition time (rise to fall) t t 1515ns refresh period t ref 64 64 ms notes: 1. ac measurement assumes t t = 1 ns. reference level for timing of input signals is 1.5 v. 2. access time is measured at 1.5 v. load condition is c l = 50 pf. 3. t lz (min) defines the time at which the outputs achieves the low impedance state. 4. t hz (max) defines the time at which the outputs achieves the high impedance state. 5. t ces defines cke setup time to ck rising edge except power down exit command. test conditions ? input and output timing reference levels: 1.5 v ? input waveform and output load: see following figures t t 2.4 v 0.4 v 0.8 v 2.0 v input t t dq cl
HB52F649E1-75b data sheet e0021h10 13 relationship between frequency and minimum latency HB52F649E1-75b parameter 133 100 frequency (mhz) ce latency = 4 ce latency = 3 t ck (ns) symbol pc100 symbol 7.5 10 notes active command to column command (same bank) i rcd 321 active command to active command (same bank) i rc 97= [i ras + i rp ] 1 active command to precharge command (same bank) i ras 651 precharge command to active command (same bank) i rp 321 write recovery or data-in to precharge command (same bank) i dpl tdpl 1 1 1 active command to active command (different bank) i rrd 221 self refresh exit time i srex tsrx 2 2 2 last data in to active command (auto precharge, same bank) i apw tdal 4 3 = [i dpl + i rp ] self refresh exit to command input i sec 97= [i rc ] 3 precharge command to high impedance i hzp troh 4 3 last data out to active command (auto precharge) (same bank) i apr 00 last data out to precharge (early precharge) i ep 3 2 column command to column command i ccd tccd 1 1 write command to data in latency i wcd tdwd 1 1 dqmb to data in i did tdqm 1 1 dqmb to data out i dod tdqz 3 3 cke to ck disable i cle tcke 2 2 register set to active command i rsa tmrd 1 1 s to command disable i cdd 00 power down exit to command input i pec 11 notes: 1. i rcd to i rrd are recommended value. 2. be valid [desl] or [nop] at next command of self refresh exit. 3. except [desl] and [nop]
HB52F649E1-75b data sheet e0021h10 14 pin functions ck0 to ck3 (input pin): ck is the master clock input to this pin. the other input signals are referred at ck rising edge. s0 , s2 (input pin): when s is low, the command input cycle becomes valid. when s is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. re , ce and w (input pins): although these pin names are the same as those of conventional drams, they function in a different way. these pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. for details, refer to the command operation section. a0 to a12 (input pins): row address (ax0 to ax12) is determined by a0 to a12 level at the bank active command cycle ck rising edge. column address (ay0 to ay9, ay11) is determined by a0 to a9, a11 level at the read or write command cycle ck rising edge. and this column address becomes burst access start address. a10 defines the precharge mode. when a10 = high at the precharge command cycle, all banks are precharged. but when a10 = low at the precharge command cycle, only the bank that is selected by ba0/ba1 (ba) is precharged. ba0/ba1 (input pin): ba0/ba1 are bank select signal (ba). the memory array is divided into bank 0, bank 1, bank 2 and bank 3. if ba1 is low and ba0 is low, bank 0 is selected. if ba1 is high and ba0 is low, bank 1 is selected. if ba1 is low and ba0 is high, bank 2 is selected. if ba1 is high and ba0 is high, bank 3 is selected. cke0 (input pin): this pin determines whether or not the next ck is valid. if cke is high, the next ck rising edge is valid. if cke is low, the next ck rising edge is invalid. this pin is used for power-down and clock suspend modes. dqmb0 to dqmb7 (input pins): read operation: if dqmb is high, the output buffer becomes high-z. if the dqmb is low, the output buffer becomes low-z. write operation: if dqmb is high, the previous data is held (the new data is not written). if dqmb is low, the data is written. dq0 to dq63, cb0 to cb7 (input/output pins): data is input to and output from these pins. v cc (power supply pins): 3.3 v is applied. v ss (power supply pins): ground is connected. detailed operation part refer to the hm5225165b/hm5225805b/hm5225405b-75/a6/b6 datasheet (e0082h).
HB52F649E1-75b data sheet e0021h10 15 physical outline 6.35 6.35 1.00 detail b detail c detail a 0.20 0.15 2.50 0.20 1.27 3.00 typ 133.35 0.15 3.00 0.10 11.43 36.83 54.61 (63.67) a b c 1 84 front side back side 85 4.00 0.10 17.80 43.18 168 2 3.00 0.10 1.00 0.05 2.00 0.10 4.175 2.00 0.10 (datum -a-) (datum -a-) unit: mm (datum -a-) r full r full note: tolerance on all dimensions 0.15 unless otherwise specified. 127.35 0.15 component area (front) component area (back) 1.27 0.10 4.00 min 4.00 max 3.125 0.125 3.125 0.125
HB52F649E1-75b data sheet e0021h10 16 cautions 1. elpida memory, inc. neither warrants nor grants licenses of any rights of elpida memory, inc. s or any third party s patent, copyright, trademark, or other intellectual property rights for information contained in this document. elpida memory, inc. bears no responsibility for problems that may arise with third party s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, contact elpida memory, inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by elpida memory, inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. elpida memory, inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. product does not cause bodily injury, fire or other consequential damage due to operation of the elpida memory, inc. product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from elpida memory, inc.. 7. contact elpida memory, inc. for any questions regarding this document or elpida memory, inc. semiconductor products.

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